Integrated circuits are fabricated to include multiple circuits performing different functions. These circuits are physically distributed across the integrated circuit and often need to communicate with each other. The communication, therefore, is accomplished using complex, and often Iong, interconnect lines, or buses.
Rapidly increasing integration density, in combination with on-die heat dissipation problems, has motivated a strong interest in exploring low-power/low-voltage circuit methodologies, while retaining high performance. As the integration density increases, major on-chip performance bottlenecks are experienced as a result of long point-to-point interconnects between and within an integrated circuit Functional Unit Blocks (FUB's). This is primarily because interconnect capacitance per unit length, dominated by sidewall fringing and cross-coupling, increases with lateral dimension scaling.
Mixed (multiple) voltage swing based CMOS circuit techniques have been studied previously for high performance/low power on-chip data path interconnects. See for example Nakagome et al., "Sub-1-V Swing Internal Bus Architecture for Future Low-Power ULSI's", IEEE Journal of Solid-State Circuits, April 1993, pp. 414-419, and Krishnamurthy et al., "Exploring the Design Space of Mixed Swing QuadRail for Low Power Digital Circuits", IEEE Transactions on VLSI Systems, December 1997, pp. 388-400 for different mixed voltage swing based CMOS circuit techniques. The general principle behind these approaches is to suppress voltage swings across long interconnects by employing an additional pair of power supply rails (Vdd2 and Vss2). driver circuit is used to receive an input signal and provides an output signal on internal interconnect lines. The output signal is limited to voltage swings between Vdd2 and Vss2. The voltage power rails, Vdd2 and Vss2, can be externally provided, or internally generated. For a given Vdd1 and Vss1, reducing the low voltage swing Vdd2-Vss2) offers a nearly linear, to quadratic, reduction in interconnect power depending on how the additional pair of power rails are generated, eg., by employing on-chip series regulation or off-chip switching regulation techniques. Providing the additional voltage supply creates a burden, particularly in low-voltage circuits. This burden is created by both area penalty of generating the power supply and penalties in routing the addition power rails throughout the integrated circuit. Further, the additional power supply must provide the drive current needed to drive long bus lines. Thus, a low voltage, high current second power supply would be needed.
For the reasons stated above, and for other reasons stated below which will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need in the art for a driver circuit for on-chip interconnects which does not require an additional power supply, but reduces interconnect voltage swing and power consumption, while improving the speed performance of the interconnect.